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DTSTART;TZID=America/Chicago:20221115T083000
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UID:submissions.supercomputing.org_SC22_sess250_drs106@linklings.com
SUMMARY:Task Scheduling on FPGA-Based Accelerators without Partial Reconfi
 guration
DESCRIPTION:Doctoral Showcase, Posters\n\nTask Scheduling on FPGA-Based Ac
 celerators without Partial Reconfiguration\n\nJungblut\n\nIn contrast to c
 onventional integrated circuits, Field Programmable Gate Arrays (FPGAs) ca
 n be reconfigured dynamically. This flexibility unlocks potential for FPGA
 -based accelerators to offload tasks in HPC.  Scheduling tasks on FPGAs is
  equivalent to the allocation of chip resources: each offloaded task occup
 ies chip area during its execution.  Hence, task scheduling on FPGAs is ty
 pically done with Partial Reconfiguration (PR). However, PR requires a hig
 h development overhead, requires expert knowledge and has limited portabil
 ity, making it difficult to apply existing research and lowering the adopt
 ion of FPGAs in HPC. We want to aid software developers and vendors to int
 egrate accelerators based on FPGAs without these issues and ask: how we ca
 n optimize task scheduling on FPGAs without relying on PR?\n\nWe answer th
 is question with three key contributions: first, we introduce an abstracti
 on-agnostic methodology to analyze and compare scheduling strategies for F
 PGAs. Center of our method is the derivation of scheduling constraints fro
 m a machine model representing a target FPGA. The schedules generated for 
 HPC applications are compared for two models. We show that the overhead fo
 r avoiding PR is feasible. Second, we propose algorithms to generate recom
 mendations for minimal changes to the program that affect the quality of p
 ossible schedules. We show that effective recommendations can be generated
  for HPC applications. Third, we contribute two polynomial-time scheduling
  algorithms. Our results can help vendors to provide significantly more st
 reamlined workflows for programming FPGAs, making the platform more appeal
 ing and helping the adoption of high-level programming environments like O
 penCL for FPGAs.\n\nRegistration Category: Tech Program Reg Pass, Exhibits
  Reg Pass
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