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DTSTART:19700308T020000
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DTSTAMP:20230124T171527Z
LOCATION:D220
DTSTART;TZID=America/Chicago:20221113T090000
DTEND;TZID=America/Chicago:20221113T093000
UID:submissions.supercomputing.org_SC22_sess430_ws_llvmf106@linklings.com
SUMMARY:Reinforcement Learning Strategies for Compiler Optimization in Hig
 h Level Synthesis
DESCRIPTION:Workshop\n\nReinforcement Learning Strategies for Compiler Opt
 imization in High Level Synthesis\n\nShahzad, Herbordt\n\nHigh Level Synth
 esis (HLS) offers a possible programmability solution for FPGAs but curren
 tly delivers far lower hardware quality than circuits written using Hardwa
 re Description Languages (HDLs).  One reason is because the standard set o
 f code optimizations used by CPU compilers, such as LLVM, are not well sui
 ted for an FPGA backend. \n\nWhile much work has been done employing reinf
 orcement learning for compilers in general, that directed toward HLS is li
 mited and conservative.  We expand both the number of learning strategies 
 for HLS compiler tuning and the metrics used to evaluate their impact.  Ou
 r results show improvements over state-of-art for each standard benchmark 
 evaluated and learning quality metric investigated.  Choosing just the rig
 ht strategy can give an improvement of 23x in learning speed, 4x in perfor
 mance potential, 3x in speedup over -O3, and has the potential to largely 
 eliminate the fluctuation band from the final results.\n\nSession Format: 
 Recorded\n\nRegistration Category: Workshop Reg Pass
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