BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20230124T171526Z
LOCATION:D222
DTSTART;TZID=America/Chicago:20221113T153000
DTEND;TZID=America/Chicago:20221113T160000
UID:submissions.supercomputing.org_SC22_sess436_ws_mchpc102@linklings.com
SUMMARY:Evaluating Emerging CXL-Enabled Memory Pooling for HPC Systems
DESCRIPTION:Workshop\n\nEvaluating Emerging CXL-Enabled Memory Pooling for
  HPC Systems\n\nWahlgren, Gokhale, Peng\n\nCurrent HPC systems provide mem
 ory resources tightly coupled with compute nodes. But HPC applications are
  evolving – diverse workloads demand different memory resources to achieve
  both high performance and utilization. In this study, we evaluate a memor
 y subsystem leveraging CXL-enabled memory to provide configurable capacity
  and bandwidth. We propose an emulator to explore the performance impact o
 f various memory configurations, and a profiler to identify optimization o
 pportunities. We evaluate the performance of seven HPC workloads and six g
 raph workloads on the emulated system. Our results show that three and two
  HPC workloads have less than 10% and 18% performance impact on 75% pooled
  memory. Also, a dynamically configured high-bandwidth system could effect
 ively support bandwidth bottle-necked workloads like grid-based solvers. F
 inally, we identify interference through shared memory pools as a practica
 l challenge for HPC systems to adopt CXL-enabled memory.\n\nSession Format
 : Recorded\n\nRegistration Category: Workshop Reg Pass
END:VEVENT
END:VCALENDAR
