BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20230124T171526Z
LOCATION:C144-145
DTSTART;TZID=America/Chicago:20221118T091000
DTEND;TZID=America/Chicago:20221118T093000
UID:submissions.supercomputing.org_SC22_sess445_ws_ia116@linklings.com
SUMMARY:Page-Address Coalescing of Vector Gather Instructions for Efficien
 t Address Translation
DESCRIPTION:Workshop\n\nPage-Address Coalescing of Vector Gather Instructi
 ons for Efficient Address Translation\n\nTakayashiki, Sato, Komatsu, Kobay
 ashi\n\nVector gather instructions are available in various processors, wh
 ich are essential for handling irregular memory accesses. Additionally, th
 e processors support virtual memory that allows programmers not to conside
 r the limitation of the physical memory space. To realize the virtual memo
 ry, the processors require address translation between virtual and physica
 l addresses. When a vector gather instruction loads data elements distribu
 ted over the physical memory space, all virtual addresses must be translat
 ed one by one, causing many translations by accessing a Translation Lookas
 ide Buffer (TLB). Hence, the TLB easily becomes a bottleneck in handling v
 ector gather instructions. To relieve the bottleneck, this paper proposes 
 an address coalescing method for the address translations of vector gather
  instructions by utilizing vector arithmetic units in the processor. The e
 valuation results show that the proposed method can achieve a 2x performan
 ce improvement in numerical and 1.08x in graph applications, which contain
  many vector gather instructions.\n\nSession Format: Recorded\n\nTag: Acce
 lerator-based Architectures, Algorithms, Architectures, Big Data, Data Ana
 lytics, Parallel Programming Languages and Models, Productivity Tools\n\nR
 egistration Category: Workshop Reg Pass
END:VEVENT
END:VCALENDAR