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DTSTAMP:20230124T171527Z
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DTSTART;TZID=America/Chicago:20221114T143000
DTEND;TZID=America/Chicago:20221114T144500
UID:submissions.supercomputing.org_SC22_sess453_ws_pmbss105@linklings.com
SUMMARY:An Initial Evaluation of Arm's Scalable Matrix Extension
DESCRIPTION:Workshop\n\nAn Initial Evaluation of Arm's Scalable Matrix Ext
 ension\n\nWilkinson, McIntosh-Smith\n\nExpanding upon their Scalable Vecto
 r Extension (SVE), Arm have introduced the Scalable Matrix Extension (SME)
  to improve in-core performance for matrix operations such as matrix multi
 plication. With the lack of hardware and cycle-accurate simulations availa
 ble which supports SME, it is unclear how effective this new instruction s
 et extension will be, and for what type of applications it will provide th
 e most benefit.\n\nBy adapting The Simulation Engine (SimEng) from the Uni
 versity of Bristol’s High Performance Computing Group to support SME, we a
 im to compare the simulated performance of a Fujitsu A64FX core (with nati
 ve SVE support) to a like-for- like hypothetical core with added SME suppo
 rt. By simulating a wide range of Streaming Vector Lengths for our hypothe
 tical SME core model, we provide and discuss first-of-a-kind results for a
 n SME implementation, before discussing future work that will be carried o
 ut to further evaluate the suitability of SME.\n\nSession Format: Recorded
 \n\nTag: Applications, Architectures, Benchmarking, Exascale Computing, Mo
 deling and Simulation, Performance, Performance Portability\n\nRegistratio
 n Category: Workshop Reg Pass
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