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DTSTAMP:20230124T171524Z
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DTSTART;TZID=America/Chicago:20221114T103000
DTEND;TZID=America/Chicago:20221114T111000
UID:submissions.supercomputing.org_SC22_sess456_misc201@linklings.com
SUMMARY:Navigating the Perils of Ubiquitous Heterogeneity
DESCRIPTION:Workshop\n\nNavigating the Perils of Ubiquitous Heterogeneity\
 n\nGokhale\n\nHeterogeneity is, and has long been, a defining characterist
 ic of computing architectures. For example, the microarchitecture implemen
 ting an instruction set architecture (ISA) contains a diverse collection o
 f function blocks such as  instruction decoder, ALUs, memory controllers, 
 page walk hardware, to name just a few. Even at the ISA level, heterogenei
 ty is available in instructions to control specialized units such as SIMD 
 or vector processors, bit matrix multiply, and crypto engines.\n\nIn the p
 ast, application developers were largely shielded from these forms of hete
 rogeneity through ISA, compiler analysis, intrinsics, or high level pragma
 s. However as microelectronics approaches fundamental scaling limits in fe
 ature size and power, it has become increasingly necessary to provide and 
 expose specialized circuits purpose-built, each to its narrow function. Th
 us, heterogeneity has become the new normal in the world of computing, aff
 ecting virtually all levels from IoT to supercomputer.\n\nIn this talk, I 
 will discuss current and future heterogeneous architectures that we will h
 ave to exploit to achieve required performance levels. Approaches and tool
 s to make these complex resources accessible will be reviewed. Scalability
  challenges and the tension between portability and performance will be di
 scussed.\n\nSession Format: Recorded\n\nRegistration Category: Workshop Re
 g Pass
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